In communication systems it is often a requirement of the receiver to determine the timing the received signal. The signal received is sampled and the timing is extracted based on some criteria. For example, in a Bluetooth receiver, a correlator is operative to correlate the received signal against a known access code and to generate a trigger when a correlation threshold is exceeded. The trigger signal is subsequently used to derive the receive timing of the remainder of the message.
Such a correlator typically uses an oversampling clock that is some multiple (e.g., 8×, 16×, etc.) of the Bluetooth bit rate of 1 Mbps. A block diagram illustrating a prior art sampling clock generator circuit suitable for use in a Bluetooth receiver is shown in FIG. 1. The circuit, generally referenced 10, comprises reference registers 22 for storing the access code, an input data shift register 20, a clock source 12, programmable frequency divider 14, Phase Locked Loop (PLL) 16, and compare circuitry 24 for generating a correlation result.
The oversampling clock 18 normally requires a PLL or an external clock at a multiple of the Bluetooth bit rate. For example, a clock source of 13 MHz is divided by a divide by 13 frequency divider before being input to the PLL. The PLL functions to generate an 8 MHz oversampling clock which is used to sample the input received signal eight times for each symbol period. In this example, the access code is 64 symbols long, thus requiring a 512 long shift register in the correlator for holding 64×8 input samples. The timing is recovered by looking for a maximum in the correlation result. Once the timing is recovered, the remainder of the packet can be recovered with ±⅛ bit resolution. It is desirable to sample the input data at a resolution of about ⅛ bit in order to provide sufficient timing resolution and minimize the bit-error-probability (BER) for the entire packet of the received data.
A disadvantage of this timing recovery scheme is the requirement to use the frequency divider and PLL to generate the sampling timing. Depending on the implementation, both components take up valuable ‘real estate’ either in board or in chip space. It is desirable to be able to eliminate both the frequency divider and the PLL especially if the reference frequency clock source is an odd frequency that is not a multiple of the Bluetooth symbol rate. This is because in this case, the realization of a frequency divider and PLL able to handle odd frequencies that are not a multiple of the Bluetooth rate becomes substantially complex.
Other disadvantages of the use of the frequency divider and PLL, which are typically realized using analog circuitry, are that (1) the use of analog circuitry results in sensitivity to variations typically encountered in chip fabrication processes that require compensation thus reducing the yield and increasing the cost, (2) current consumption is increased, (3) silicon size or board space is increased, (4) development time is increased, and (5) the migration to more advanced semiconductor processes becomes more difficult in comparison with purely digital implementations.
There is therefore a need for a purely digital oversampling clock scheme that is capable of generating the sampling instance timing, such that the resulting timing accuracy is not affected. In addition, it is desirable to realize such an oversampling clock scheme that would be capable of deriving the required oversampling timing from a wide range of arbitrary reference clock frequencies, thereby eliminating the need for a dedicated clock source with its associated cost and size.